The escalating demands for high density and performance associated with non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology and often makes it difficult for the memory device to meet its expected data retention requirement.
For example, charge leakage may occur from one or more memory cells of the memory device due to poor quality interlayer dielectrics that may include voids. Such charge leakage may result in the memory device being unable to meet the expected data retention requirement and, ultimately, may lead to device failure.